Calculating power semiconductor losses in an inverter requires more than multiplying a datasheet resistance by the rated current. Conduction paths change throughout the electrical cycle, switching energy depends on the commutation conditions and junction temperature changes the parameters used in the calculation.

A useful model connects those effects without counting the same energy twice. The method below covers a two-level, three-phase inverter, with equations for MOSFETs and IGBTs, a worked MOSFET example and a practical route from electrical losses to thermal validation.

Define the operating envelope first

Start with the conditions the inverter must survive, not just its nominal output power. Record DC-link voltage, phase-current waveforms, switching frequency, modulation strategy, dead time, gate-drive settings and cooling conditions. Include overloads, regeneration, low-speed operation and maximum ambient temperature where relevant.

Use phase current at the switching bridge, including significant ripple. Motor nameplate current or DC-link average current is not a substitute. Define whether your calculation represents continuous operation, a short overload or a complete mission profile.

Also establish the calculation boundary: one transistor, one half-bridge or the complete inverter. Keep transistor, diode and non-semiconductor losses separately identifiable.

If device selection is still open, these inputs also support selecting devices for reliable motor drives. A comparison is meaningful only when each candidate is evaluated against the same electrical and thermal requirements.

Calculate power semiconductor conduction losses

MOSFETs: integrate the actual channel current

For a first-order calculation with resistance held at a representative junction temperature:

P_cond = R_DS(on)(T_j) × I_ch,rms²
I_ch,rms² = (1/T) × ∫[g_ch(t) × i_phase(t)²] dt

Here, T is the evaluation period and g_ch(t) is one when that device’s channel carries current and zero otherwise. The RMS calculation covers the entire evaluation period, including intervals when the device carries no current.

Include reverse channel conduction when synchronous rectification is enabled. Exclude intervals assigned to body-diode conduction, otherwise the same current interval will appear in two loss terms.

Use on-resistance at the expected junction temperature and actual gate voltage. A room-temperature typical value can materially understate conduction loss. Nexperia’s guide to MOSFET datasheet parameters explains the distinction between specified parameters, characteristic curves and their test conditions.

For an ideal balanced three-phase inverter with sinusoidal current, centred sinusoidal PWM and continuous synchronous rectification, neglecting dead time:

I_ch,rms per transistor = I_phase,rms / √2
P_cond,total = 3 × I_phase,rms² × R_DS(on)

These shortcuts assume identical devices and symmetrical operation. Current ripple, discontinuous modulation, pulse suppression or unequal current sharing require waveform-based integration instead. The relevant current is the RMS current through each channel, not the phase-current peak multiplied by a nominal duty ratio.

IGBTs: separate transistor and diode conduction

For an IGBT, power semiconductor conduction loss is better represented by a voltage-drop model than by a single resistance:

P_cond,IGBT ≈ V_CE0(T_j) × I_C,avg
              + r_CE(T_j) × I_C,rms²

Fit the intercept V_CE0 and slope r_CE to the output characteristic over the relevant current range. Both current quantities must include only that transistor’s conduction intervals, averaged over the full evaluation period.

Calculate the antiparallel diode separately using its forward-voltage characteristic. A comparable linear approximation uses V_F0 × I_D,avg + r_D × I_D,rms². Do not use signed phase-current averages, which can cancel to zero despite substantial dissipation.

Modulation index and power factor affect how current is shared between IGBT and diode. Regeneration can therefore produce a different thermal distribution from motoring at the same phase-current RMS value. Device-level loss estimates matter even when total bridge losses look similar.

The same bookkeeping applies across technologies, but the mechanisms differ. Silicon carbide MOSFETs still require reverse-conduction and output-capacitance accounting. Enhancement-mode GaN devices do not have a silicon-style PN body diode, yet their reverse-conduction intervals are not loss-free. Neither technology justifies removing commutation losses from the model without supporting measurements or validated device data.

Calculate switching losses from event energy

For each power semiconductor, sum the energy dissipated during its actual switching events:

P_sw = Σ(E_on,n + E_off,n) / T_eval

For fixed-frequency PWM, this is often expressed as:

P_sw = f_sw × average(E_on + E_off)

The average must cover every carrier cycle in the evaluation period, including cycles with soft commutation or no switching. Alternatively, count only active events and use their actual occurrence rate. Do not mix the two conventions.

Obtain switching energy at the relevant blocking voltage, instantaneous current, junction temperature, gate voltage and gate resistance. Datasheet energy curves or a validated device model provide a starting point. Interpolate within supported data; treat simple proportional voltage or current scaling as an approximation, not a universal device law.

In a sinusoidal inverter, evaluate energy across the fundamental cycle. Reading one energy value at phase-current RMS does not reproduce this average. For illustration, a 20 A RMS sine wave has a 28.3 A peak, while its average current magnitude is approximately 18.0 A. Neither number automatically represents the correct switching-energy operating point because energy is generally nonlinear with current.

IGBT turn-off energy includes tail-current effects under the stated test conditions. For MOSFETs, package inductance, commutation-loop inductance and the gate-drive circuit can materially change measured energy. Changing gate resistance to improve EMC therefore requires a fresh loss assessment.

Account for recovery, capacitance and dead time once

A power semiconductor loss budget needs explicit rules for allocating commutation energy. Turn-on energy measured in a hard-switched half-bridge may already contain the additional transistor dissipation caused by the opposite diode’s reverse recovery. Adding an independent recovery estimate without checking the measurement boundary can double-count part of that loss.

Likewise, output-capacitance energy may already be represented in measured switching waveforms or a simulation model. Nonlinear capacitance means that a constant-capacitance ½CV² approximation can also be misleading. Use the manufacturer’s energy definition and identify where that energy is dissipated or recovered in your topology.

Dead-time conduction remains a separate interval-based calculation. For a balanced three-phase bridge with two dead-time intervals per carrier period, continuous PWM and approximately constant reverse voltage:

P_dead,total ≈ 3 × 2 × f_sw × t_dead × V_rev × average(|i_phase|)
average(|i_phase|) = (2√2/π) × I_phase,rms

This approximation assumes current changes little during each dead-time interval. Use actual diode or reverse-channel voltage characteristics for a more accurate calculation, particularly near current zero crossings.

Dead time replaces part of normal channel conduction. If the channel-loss estimate initially assumes conduction throughout the carrier period, subtract the displaced channel loss before adding the dead-time term. Diode forward-conduction energy and reverse-recovery energy are different mechanisms, but both must be checked against the boundaries of any measured switching-energy data.

Worked example: a three-phase MOSFET inverter

The following power semiconductor loss calculation uses illustrative inputs, not the specifications of a particular component. Assume balanced sinusoidal currents, identical MOSFETs and continuous synchronous PWM. Neglect current ripple for this first pass.

Input	Assumed value	Calculation boundary
DC-link voltage	400 V	Bridge input
Phase current	20 A RMS	Each phase
Switching frequency	20 kHz	Each switch position
MOSFET count	6	Complete bridge
Hot on-resistance	45 mΩ	Each MOSFET
Dead time	500 ns	Each transition
Reverse-conduction voltage	3.0 V	Dead-time approximation
Average switching energy	0.30 mJ	Per MOSFET, per carrier cycle

The 0.30 mJ value represents E_on + E_off averaged over the entire fundamental cycle for each transistor. It includes the relevant low-loss and hard-switching commutations, not just the hard-switched half-cycle. Assume it accounts for the transistor’s relevant recovery-related and capacitive switching dissipation, so no additional lumped switching term is added.

This energy value would need to come from waveform-resolved modelling or measurements for a real design. It cannot be inferred from voltage rating, on-resistance or material type alone.

For conduction, the ideal channel-loss result is 3 × 20² × 0.045 = 54 W. Under the stated assumptions, two dead-time intervals occupy 2 × 20,000 × 500 ns = 0.02, or 2% of each carrier period. Applying that first-order channel-occupancy correction gives 54 × 0.98 = 52.92 W.

Sum the losses at a consistent boundary

The total power semiconductor loss now combines corrected channel conduction, switching and dead-time conduction. Switching loss across all six devices is:

P_sw,total = 6 × 20,000 × 0.00030 = 36.0 W

The sinusoidal average current magnitude is approximately 18.0 A. Dead-time conduction is therefore:

P_dead,total ≈ 3 × 2 × 20,000 × 500 ns × 3.0 × 18.0
             ≈ 3.24 W

Loss mechanism	Complete bridge	Per MOSFET, assuming symmetry
Channel conduction	52.92 W	8.82 W
Switching	36.00 W	6.00 W
Dead-time conduction	3.24 W	0.54 W
Total	92.16 W	15.36 W

Keeping the original 54 W channel estimate and simply adding dead-time losses would overstate this model by 1.08 W. That difference is modest here, but it demonstrates why conduction intervals must remain consistent.

These figures represent device heat, not complete inverter losses. Gate-drive supplies, DC-link capacitors, busbars, PCB copper, filters and control electronics need separate budgets. Their heat may still affect the same enclosure or cooling system.

The calculation also exposes useful design sensitivities. Increasing switching frequency raises the switching term approximately proportionally only if event energy remains unchanged. Lowering on-resistance reduces conduction loss, but an alternative device may have different capacitance and switching energy. Compare complete operating-point losses rather than optimising a single datasheet parameter.

Convert power semiconductor loss into junction temperature

For six equally loaded devices on a shared heatsink, a simplified steady-state model is:

T_sink = T_ambient + P_total × R_θSA
T_j,k = T_sink + P_device,k × (R_θJC + R_θCS)

Assume an ambient temperature of 50°C, heatsink-to-ambient resistance of 0.35 K/W and a combined junction-to-case plus case-to-sink resistance of 1.2 K/W per device:

T_sink ≈ 50 + 92.16 × 0.35 = 82.3°C
T_j ≈ 82.3 + 15.36 × 1.2 = 100.7°C

This approximately 101°C result is conditional on the assumed cooling performance. The shared heatsink rise depends on total heat, while the local junction-to-sink rise depends on the individual device’s dissipation.

Real assemblies can have uneven airflow, mounting-pressure variation, thermal-interface ageing and coupling between adjacent devices. A single heatsink temperature is then insufficient. Also avoid substituting datasheet junction-to-ambient resistance for a mounting-specific thermal network.

For short overloads, use transient thermal impedance rather than steady-state thermal resistance. For a single power step, junction rise can be estimated using ΔT_j(t) = P_step × Z_θ(t) under the model’s boundary conditions. Arbitrary load profiles require thermal-network simulation or superposition of power steps. Nexperia’s RC thermal-model guidance provides background on these models.

When the inverter operates inside a sealed product, thermal management for sealed enclosures also becomes part of the calculation boundary.

Iterate temperature and evaluate operating corners

A power semiconductor loss model is not complete after one pass because electrical losses and junction temperature are coupled. Start with a plausible junction temperature, calculate losses, solve the thermal model and update the temperature-dependent parameters. Repeat until the result is sufficiently stable for the design decision.

In the example, the assumed hot on-resistance should correspond to approximately 101°C at the applied gate voltage. If it instead represents 75°C, update it and recalculate. Treat switching energy and diode voltage with the same discipline. Their temperature dependence is device-specific and should not be replaced by a generic percentage correction.

For GaN devices, assess whether dynamic on-resistance under the intended switching conditions needs to be represented. For parallel devices, include unequal current sharing and thermal coupling rather than dividing the bridge loss evenly by device count.

Evaluate operating corners individually. High current can dominate conduction loss, while high DC-link voltage can increase switching loss. Poor cooling can create the highest junction temperature without producing the highest electrical loss. Low-speed motor operation may also concentrate heating in particular devices over thermally significant intervals.

Use guaranteed limits where available and justified allowances where parameters are only characterised typically. Keep normal operation, repetitive overload and fault conditions separate. A steady-state loss calculation does not establish short-circuit withstand capability, protection response or safe operating area. Those require their own checks against device limits and system behaviour.

Validate the model before freezing the design

Validate power semiconductor losses against the actual gate drive, PCB layout and commutation loop. A low-inductance laboratory fixture can produce different switching energy from the production assembly, particularly after gate-resistance changes or the addition of snubbers.

A practical validation programme should include:

• Double-pulse measurements at representative voltage, current and temperature, using voltage and current probes with adequate bandwidth and corrected timing alignment.
• Continuous-operation thermal measurements with representative cooling, mounting and enclosure conditions, supported by a method for estimating junction temperature.
• Corner testing that covers relevant overloads, regeneration, switching-frequency modes and protection transitions.

Switching-energy measurement is sensitive to probe delay: a small timing mismatch between voltage and current can materially distort the integral of instantaneous power. Identify integration windows and distinguish semiconductor dissipation from energy temporarily stored in parasitic elements. High-voltage measurements require appropriately rated equipment and safe laboratory procedures.

Compare predictions and measurements at several operating points, not only nominal load. Agreement at one point can conceal compensating errors, such as underestimated switching loss and overestimated thermal resistance. Update the model with measured dependencies before using it to justify reduced cooling capacity or higher current.

Keep firmware settings within this validation boundary. Dead time, pulse suppression, switching frequency and fault handling all change device stress. Record the tested configuration alongside the hardware revision so that later software changes trigger the appropriate engineering review. Electrical efficiency testing alone does not demonstrate EMC compliance, electrical safety or long-term reliability.

Frequently asked questions

Can I calculate power semiconductor losses from measured inverter efficiency? Input power minus output power gives total inverter loss, subject to measurement accuracy. It does not separate transistor losses from capacitor, conductor, filter or auxiliary losses. At high efficiency, small power-measurement errors can become a large percentage of the inferred loss. Use it as a system-level cross-check rather than the only device-level calculation.

Should I use typical or maximum datasheet values? Typical curves are useful for initial estimates and comparisons. Release decisions need a documented treatment of production variation, temperature, gate-drive tolerance and model uncertainty. Maximum on-resistance may be specified, while maximum switching energy may not be. A fixed percentage margin is not a substitute for understanding those differences.

Does a lower switching frequency always improve the design? It usually reduces switching-event loss if other conditions remain comparable, but it can increase current ripple, acoustic noise or filter requirements. Recalculate RMS current and assess control performance, passive components and EMC alongside semiconductor heating. The lowest transistor-loss operating point is not necessarily the best system design.

Can a case-temperature measurement replace junction-temperature analysis? No. It provides a useful thermal boundary measurement, but the junction remains hotter by an amount determined by device dissipation and the relevant thermal path. Transient operation also requires the thermal history to be considered.

Turn the calculation into a production-ready design

A useful power semiconductor loss model should identify the assumptions that still need evidence: switching energy in the real commutation loop, hot conduction characteristics, cooling performance and firmware-dependent operating modes.

ProMicro combines power electronics, analogue electronics, embedded systems and firmware with PCB design, prototyping and manufacturing support. That integrated approach helps connect component calculations to the physical product and its operating environment.

If your team needs specialist capacity, discuss a review of the loss model, thermal assumptions and validation plan with ProMicro. Its approach to designing power electronics for reliability, EMC and scale places those calculations within a broader development process, with compliance and qualification requirements considered from the outset.